The present invention relates to a method of modifying an integrated circuit, in particular through a series of scaling operations.
In particular, but not exclusively, the invention relates to a process by which the physical design or layout of an integrated circuit or subcircuit can be modified to meet a different set of design and manufacturing rules. This method involves analysing data of the existing integrated circuit to determine the scaling factor then altering the shapes in the original by scaling the data, scaling individual layers, adjusting the edges of shapes and swapping geometries and cells through a defined sequence, according to a process migration technique.
Process migration is a technique for modifying integrated circuit designs so that they can be manufactured by new manufacturing processes with different geometric sizes and relationships. The physical size of an integrated circuits is limited by the manufacturing process used. The limiting factor is the size of the smallest component that can be produced, which at present is approximately 0.13 microns.
As new processes are devised, components can be manufactured to smaller sizes. However, before an existing circuit can be built at a smaller scale using a new manufacturing process, the circuit layout must be re-designed. The overall plan of the circuit may be approximately the same, but different parts and components of the circuit may need to be scaled by differing factors. There are rules governing these critical dimensions. Some rely on manufacturing constraints, for example the smallest feasible size of a connection, whereas others depend on electronic factors such as capacitance and resistance.
When re-designed, computers can check the circuits for compliance with these design rules.
There may be various reasons for switching to a new manufacturing process, including:
1) SPEED: smaller components have faster switching due to smaller charge transfer requirements and smaller sing distances.
2) SIZE: unit costs are lower, as more chips can be made per silicon wafer
3) ECONOMIC PRODUCTION: more products can be made on one production line, allowing older, less economical, production lines to be closed.
The main problem is how to modify the physical design of the circuit. This can be very difficult and complicated.
Another reason for re-designing the chips is that many circuits are now designed using parts or components supplied by different manufacturers, called xe2x80x9csystem-on-chipxe2x80x9d components. However, these components may be produced by different manufacturers and made to different design rules, and need to be re-designed so that they all comply to the same set of design rules.
Reasons for re-designing might therefore include:
1) Compliance with particular design rules;
2) To make use of the latest manufacturing processes; and
3) To reduce the size of the component by a certain factor.
Existing methods of process migration are as follows:
Symbolic Migration. In this, each component, such as each transistor, is re-generated according to required technical specifications. The process is not very successful especially for complicated circuits.
Compaction. It is known, for example from U.S. Pat. No. 5,640,497, to provide a method of redesigning layouts. In this method, the circuit is made smaller by squeezing all the dimensions to the smallest allowed by the design rules, first in the x direction and then in the y direction. The technique is partially successful, but xe2x80x9cflattensxe2x80x9d the circuit: i.e. it destroys the hierarchy of the building blocks. This requires huge computing power to achieve and, because the hierarchy can no longer be identified, it makes subsequent modification extremely difficult.
Scaling. Scaling implies reducing the size of each component by a constant factor. While this reduces the size of the component, the resulting circuit will generally be inoperable as it is likely to break many hundreds of thousands of design rules. Therefore, while this is sometimes seen as the ideal solution, it has not previously been achievable.
It is an object of the present invention to provide a method of scaling an integrated circuit that mitigates at least some of the aforesaid problems.
According to the present invention there is provided a method of modifying an integrated circuit, the method including the steps of selecting a scaling factor, scaling the circuit according to the scaling factor, and adjusting the circuit for functionality and design rule compliance.
The method makes it possible to scale a circuit without losing functionality or destroying the hierarchy of the circuit.
Advantageously, the scaling factor is selected by calculating a plurality of predetermined scaling ratios and selecting a scaling factor that is equal to or greater than the largest of the predetermined scaling ratios. This ensures that the circuit is scaled to the maximum degree without violating essential design rules. Advantageously, the predetermined scaling ratios include the interconnect scaling ratio, the via size ratio and the electrical component geometry ratio.
Advantageously, the scaling factor is selected by rounding up to the next whole grid point from the largest of the predetermined scaling ratios. This ensures that the components of the circuit are placed correctly on the design grid.
Advantageously, the step of scaling the circuit according to the scaling factor circuit includes multiplying the co-ordinates of the circuit geometry by the scaling factor.
Advantageously, the step of adjusting the circuit for functionality and design rule compliance includes a hierarchical layer scaling process. The hierarchical layer scaling process may include the step of scaling the components in a layer according to a predetermined layer scaling factor. This may be achieved by absolute scaling (adding or subtracting a fixed amount to the size of each component), or alternatively by relative scaling (multiplying to increase or decrease the size of each component by a fixed percentage of its original size). The hierarchical layer scaling process may include the step of scaling the components so as to maintain the connectivity of those components. The hierarchical layer scaling process may include the step of identifying components that meet predetermined width criteria, and scaling only components that do not meet those criteria. In this way, power connectors can be excluded from the scaling process, to avoid overheating problems.
Advantageously, the step of adjusting the circuit for functionality and design rule compliance includes a transistor edge adjustment process. The transistor edge adjustment process may include the step of adjusting the width of the polysilicon layer and/or the length of the diffusion layer. This restores the correct dimensions of the components making up the transistors, to ensure functionality.
Advantageously, the method includes the step of updating the contacts and vias. The step of updating the contacts and vias may include removing the existing contacts and vias and replacing them with new contacts and vias, to reduce current density.
Advantageously, the method includes the step of adding and/or deleting layers, to accommodate changes in technology.
Advantageously, the method includes the step of checking the circuit using a layout verification process to ensure compliance with design rules.
Advantageously, the method includes the preliminary step of analysing and modifying the circuit data, to reduce the time needed to complete the migration process
Advantageously, the method includes the step of adding nodes containing design parameters to devices in the circuit, so allowing easy access to information about those devices.
It is a further object of the present invention to provide a different process migration technique which may be described as xe2x80x9ccomplex scalingxe2x80x9d and which is applicable to the computer model of the layout of any existing integrated circuit. By using this technique, the layout of a chip may be modified to be manufactured in any new process and at any scale that meets the new design rules.
The method is applicable to flat chips layouts and those containing design hierarchy, which may be defined as the placing of sub-cells into higher level circuits and these, in turn, being placed again. The hierarchy of the migrated chip matches the hierarchy of the original.
According to another aspect of the present invention, there is provided a method of scaling an integrated circuit comprising the steps of examining the existing layout to determine the amount by which the layout must be scaled, including determining variable geometry values; absolute geometry values; and a design grid, and carrying out one or more of gate width and length adjustment; layer scaling; polygon edge adjustment; contact replacement; adjust overlaps; addition or removal of layers; cell swapping; and verification.